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| ? semiconductor components industries, llc, 2010 september, 2010 ? rev. 0 1 publication order number: ncp1910/d ncp1910 high performance combo controller for atx power supplies housed in a so ? 24wb package, the ncp1910 combines a state ? of ? the ? art circuitry aimed to powering next generation of atx or flat tvs converters. with a 65 khz continuous conduction mode power factor controller and a llc controller hosting a high ? voltage driver, the ncp1910 is ready to power 85+ types of offline power supplies. to satisfy stringent efficiency considerations, the pfc circuit implements an adjustable frequency fold back to reduce switching losses as the load is going light. to cope with all the signal sequencing required by the atx and flat tvs specifications, the controller includes several dedicated pins enabling handshake between the secondary and the primary sides. these signals include a power ? good line but also a control pin which turns the controller on and off via an opto coupler. safety ? wise, a second ovp input offers the necessary redundancy in case the main feedback network would drift away. finally, a fast fault input immediately reacts in presence of an over current condition by triggering an auto ? recovery soft ? start sequence. features ? fixed ? frequency 65 khz ccm power factor controller ? average current ? mode control for low line distortion ? dynamic response enhancer reduces bulk undershoot ? independent over voltage protection sensing pin with latch ? off capability ? adjustable frequency fold back improves light load efficiency ? adjustable line brown ? out protection with 50 ms delay to help meeting hold ? up time specifications ? programmable over current threshold leads to an optimized sensing resistor ? 1 a peak current drive capability ? llc controller operates from 25 khz to 500 khz ? on board 600 v high ? voltage drivers ? 1 a/0.5 a sink/source capability ? minimum frequency precision down to 3% over temperature range ? internally fixed dead ? time value of 300 ns ? adjustable soft ? start sequence ? fast fault input with soft ? start trigger for immediate auto ? recovery protection ? on /off control pin for secondary ? based remote control ? on ? board 5 v reference voltage for precise thresholds/hysteresis adjustments ? power good output management signal ? a version with dual ground pinout (no skip), b version with single ground and skip operation for the llc controller ? 20 v operation ? these are pb ? free devices typical applications ? multi output atx power supplies (a version) ? flat tvs power supplies (b version) marking diagram so ? 24wb less pin 21 dw suffix case 752ab http://onsemi.com see detailed ordering and shipping information in the package dimensions section on page 36 of this data sheet. ordering information ncp1910xxx awlyywwg 1 xxxxx = specific device code a = assembly location wl = wafer lot yy = year ww = work week g = pb ? free package
ncp1910 http://onsemi.com 2 figure 1. pin connections gnd/pgnd ovp2 drv pg adj. v cc vref ml bo adj. on/off bridge pg out mu rt vboot ss skip/agnd fb cs/ff vctrl 124 fold lbo cs vm pin description pin n pin name function pin description 1 ss soft ? start a capacitor to ground sets the llc soft ? start duration 2 rt the llc feedback pin a resistive arrangement sets the maximum and minimum switching frequencies with opto coupler ? based feedback capabilities. 3 pg out the open ? collector power good signal this pin is low when v bulk is ok, opens when v bulk passes below a level adjusted by pgadj pin. 4 on /off remote control when pulled low, the circuit operates: the pfc starts first and once fb is in regulation, the llc is authorized to work. when left open, the controller is in idle mode. 5 bo adj. brown ? out adjustment this pin sets the on and off levels for the pfc powering the llc converter 6 vref the 5 v reference pin this pin delivers a stable voltage for threshold adjustments 7 pg adj. the power good trip level from the vref pin, a dc level sets the trip point for the pfc bulk voltage at which the pg out signal is down. 8 ovp2 redundant ovp a fully latched ovp monitoring the pfc bulk independently from fb pin. 9 fb pfc feedback monitors the boost bulk voltage and regulates it. it also serves as a quick auto ? recovery ovp 10 v ctrl pfc error amplifier output pfc error amplifier compensation pin 11 v m pfc current amplifier output a resistor to ground sets the maximum power level 12 lbo pfc line input voltage sensing line feed forward and pfc brown ? out 13 fold pfc fold back this pin selects the power level at which the frequency starts to reduce gradually. 14 cs pfc current sense this pin senses the inductor current and also programs the maximum sense voltage excursion 15 cs/ff fast ? fault input when pulled above 1 v, the llc stops and re ? starts via a full soft ? start sequence. 16 skip/agnd skip (b)/agnd (a) this pin is either used as the analog gnd for the signal circuit (a) or for skip operation (b). 17 gnd/pgnd gnd (b)/pgnd (a) the controller ground for the driving loop (a) or the lump ground pin for all circuits (b) 18 drv pfc drive signal the driving signal to the pfc power mosfet 19 v cc the controller supply the power supply pin for the controller, 20 v max. 20 ml lower ? side mosfet drive signal for the lower side half ? bridge mosfet 22 bridge half ? bridge this pin connects to the llc half ? bridge 23 mu upper ? side mosfet drive signal for the upper side half ? bridge mosfet 24 v boot bootstrapped vcc the bootstrapped v cc for the floating driver ncp1910 http://onsemi.com 3 *it is recommended to separate the traces of power ground and analog ground. the power ground (pin 17) for driving loop (pfc dr v and llc ml) is connec- ted to the pfc mosfet directly. the analog ground for adjustment components is routed together first and then connected to the analog ground pin (pin 16) and the pfc sense resistor directly. figure 2. typical application schematic in a version m1 m2 c14 l2 d6 d9 t1 c4 vout r11 r30 u1 c7 u2b r10 r18 . . . r9 r17 r8 r16 c3 over current c15 r29 d12 d11 c13 r28 1 2 3 4 5 8 6 7 9 10 13 14 15 16 17 18 19 20 11 12 22 23 24 u100 c12 r22 r12 u2a u3a c10 0.1u bulk 12 v aux. on/off fb vcc r21 vref power good c6 0.1u r14 r15 pg adj. r13 bo level r31 0.1 d4 d8 d3 d7 c5 d2 c1 l1 r19 10 d10 r20 10k r1 3.5m r2 1.5m r32 3.6k r4 2.2m r5 3.5m input line d5 d1 r23 120k c8 0.22u c2 r24 24k r3 1.5m r7 2.2m r26 24k c9 1u r25 24k r27 39k c11 1n r33 1.2k r6 vref x2 pad2 x3 v33 v32 c16 0.1u r34 8.4k c17 1n (*) (*) q1 r35 300 c18 1n ncp1910 http://onsemi.com 4 *it is recommended to separate the traces of power ground and analog ground. the analog ground traces for adjustment components are routed together first and then connected to the ground pin (pin 17). the power ground for driving loop (pfc drv and llc ml) is connected from ground pin (pin 17) to the pf c sense resistor directly and as short as possible. figure 3. typical application schematic in b version m1 m2 c14 l2 d6 d9 t1 c4 vout r11 r30 u1 c7 u2b r10 r18 . . . r9 r17 r8 r16 c3 over current c15 r29 d12 d11 c13 r28 1 2 3 4 5 8 6 7 9 10 13 14 15 16 17 18 19 20 11 12 22 23 24 u100 c12 r22 r12 u2a u3a c10 0.1u bulk 12 v aux. on/off fb vcc r21 vref power good c6 0.1u r14 r15 pg adj. r13 bo level r31 0.1 d4 d8 d3 d7 c5 d2 c1 l1 r19 10 d10 r20 10k r1 3.5m r2 1.5m r32 3.6k r4 2.2m r5 3.5m input line d5 d1 r23 120k c8 0.22u c2 r24 24k r3 1.5m r7 2.2m r26 24k c9 1u r25 24k r27 39k c11 1n r33 1.2k r6 vref x2 pad2 x3 v33 v32 c16 0.1u r34 8.4k c17 1n (*) (*) q1 r35 300 c18 1n r36 c19 skip ncp1910 http://onsemi.com 5 + ? + ? vovp vuvp 105% vpref 8% vpref pfc_opl + ? ovp2 fb 95% vpref + ? vld vpref vctrl ota vctrl(min) a b multiplier lbo cs vdd vlbo^2 ?1? bo notok, ?0? bok a b a/b ics a b vctrl ? vctrl(min) ics x vlbo^2 + ? + ? ics x vlbo > 275 ua ics > 200 ua ics sum 2 k1 k2 pfc_ol vm + ? ?0? / ?1? vpref / 10%vpref s r q q + ? vpref pfc_ovp pfc_ol tsd vlbo^2 vdd ivld dynamic response enhancer ?1? = uvp, ?0? ok closed if ?1? ?1? ovp, ?0? = ok vfold ics vdd oscillator section ict(min) drv vcc foldback pfc drive signal onoff uvlo latch rfb pull down ?1? = opl ?1? = ocp pfc_uvp the ?pfc_ok? toggles high when: ? vld is low ? pfc issues a driving pulse the ?pfc_ok? toggles low when: ? vctrl stays out of window [vctrl,min to vctrl,max] > 1 sec ? at this point, the latch is reset and the ?pfc_ok? output goes low. ?1? = below 5% reg ?0? ok auto ? recovery internal ovp + ? vovp2 107% vpref ?1? ovp2, ?0? = ok latched adjustable ovp2 pfc_ovp2 latched vctrl + ? vctrl(min) ? 0.1 v vctrl + ? 1 sec delay if pfc issues an abnormal situation, then latch off grand reset pfc_ok pfc_ok s r q q pfc_ok grand reset pfc_skip (0.6 v clamp voltage is activated.) vlbo pfc_bo + ? ilbo vlbot 20 us filter latch pfc_bo pfc_skip + ? vctrl(max) pfcflag ict vfold(max) ict(fold) s r q q pfc_ovp grand reset pfc_ocp pfc_opl grand reset ?1? open ?0? close pfc_abnormal latched pfc_bo pfc_bo pfc_bo pfc_bo + ? ?1? = fb > vpref s r q q grand reset pfc_bo figure 4. internal pfc block diagram ics vlbo 2 4 ( vctrl vctrl ( min )) bo delay ncp1910 http://onsemi.com 6 rt vref pg adj pg out cs/ff on /off bo adj vcc management uvlo hi side level shifter vrt + - s r q q clk d vboot mupper bridge vcc mlower gnd_llc delay dead time a b b a pfc_fb "1" bonot ok 20 ms delay tdel1 "1" enables llc "0" llc is locked grand reset ss + - ss_rst + - vcs1 + - vcs2 uvlo vdd vref llc_bo grand reset s r q q grand reset onoff uvlo pfc_bo grand reset grand reset grand reset r latch latch vdd rpull up on_off on/off "1" controller is off "0" controller is on gnd prop. delay matching pfc_uvp pfc_ok "1" is ok "0" notok 5 ms delay tdel2 r "1" after reset "0" when pg out drops after 5 ms pfc_ovp2 llc_bo latch pulse trigger s r clk q qn s r q q skip/gnd_pfc + - vskip skip: b version only thermal shut down tsd tsd "1" tsd is on "0" tsd is off grand reset "1" pgnot ok + - + - tbok tbonotok llc_bo llc_pg s r q q llc_pg grand reset figure 5. internal llc block diagram ncp1910 http://onsemi.com 7 maximum ratings table symbol rating value unit v bridge continuous high voltage bridge pin, pin 22 ? 1 to 600 v v boot ?v bridge floating supply voltage, pin 24 ? 22 ? 0.3 to 20 v v mu , v drv high side output voltage, pin 23 v bridge ? 0.3 to v boot + 0.3 v v ml low side output voltage, pin 18, 20 ? 0.3 to v cc + 0.3 v dv bridge /dt allowable output slew rate on the bridge pin, pin 22 50 v/ns v cc power supply voltage, pin 19 20 v pin voltage, all pins (except pin 2, 6, 18 ? 24, gnd) ? 0.3 to 10 v r ja thermal resistance junction ? to ? air 50 mm 2 , 1 oz 650 mm 2 , 1 oz 80 65 c/w storage temperature range ? 60 to + 150 c esd capability, human body model (all pins except v cc and hv) 2 kv esd capability, machine model 200 v v cc power supply voltage, pin 19 20 v pin voltage, all pins (except pin 2, 6, 18 ~ 24, gnd) ? 0.3 to 10 v v rt rt pin voltage ? 0.3 to 5 v v ref_out v ref pin voltage ? 0.3 to 7 v i max pin current on pin 10, 12, and 13 0.5 ma i pgout pin current on pin 3 5 ma stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. this device(s) contains esd protection and exceeds the following tests: human body model 2000 v per jedec standard jesd22 ? a114e machine model 200 v per jedec standard jesd22 ? a115 ? a 2. this device contains latch ? up protection and exceeds 100 ma per jedec standard jesd78. electrical characteristics (for typical values t j = 25 c, for min/max values t j = ? 40 c to +125 c, max t j = 150 c, v cc = 12 v unless otherwise noted) symbol rating pin min typ max unit common to both controllers supply section v cc(on) turn ? on threshold level, v cc going up 19 9.4 10.4 11.4 v v cc(min) minimum operating voltage after turn ? on 19 8 9 10 v v cc(hys) hysteresis between v cc(on) and v cc(min) 19 1.2 ? ? v v boot(on) startup voltage on the floating section 24,22 7.8 8.8 9.8 v v boot(min) cutoff voltage on the floating section 24,22 7 8 9 v i startup startup current, v cc < v cc(on) 19 ? ? 100 a i cc1 pfc consumption alone, drv pin unloaded, on/off pin grounded, llc off (pfc is 65 khz) 19 ? 5.1 6.4 ma i cc2 pfc consumption, drv pin loaded by 1 nf, on/off pin grounded, llc off (pfc is 65 khz) 19 ? 5.9 7.4 ma 3. in normal operation, when the power supply is un ? plugged, the bulk voltage goes down. at a first crossed level, the pg pin opens. later, when the bulk crosses a second level, the llc turns off. there is no timing link between these events, except the bulk capacitor dis charge slope. however , if for an unknown reason the pfc is disabled (fault, short ? circuit), the pg pin immediately opens and if sufficient voltage is still present on the bulk (e.g. in high line condition), the llc will be disabled after a typical time of 5 ms. 4. guaranteed by design. ncp1910 http://onsemi.com 8 electrical characteristics (for typical values t j = 25 c, for min/max values t j = ? 40 c to +125 c, max t j = 150 c, v cc = 12 v unless otherwise noted) symbol unit max typ min pin rating common to both controllers supply section i cc4 ic consumption, both pfc and llc loaded in no load conditions (pfc is 65 khz and r t = 70 k (llc is 25 khz)) 19 ? 5.9 7.2 ma i cc5 ic consumption, both pfc and llc loaded 1 nf load conditions (pfc is 65 khz and r t = 70 k (llc is 25 khz)) 19 ? 6.9 8.6 ma i cc6 ic consumption in fault mode from v boot (drivers disabled, v boot > v boot(min) ) 19 ? 64 300 a i cc7 ic consumption in off mode from v cc (on /off pin is open) 19 ? ? 950 a reference voltage v ref ? out reference voltage for external threshold setting @ i out = 5 ma 6 4.75 5 5.25 v v ref ? out reference voltage for external threshold setting @ i out = 5 ma ? t j = 25 c 6 4.9 5 5.1 v v reflinereg vcc rejection capability, i out = 5 ma ? v cc = 1 v ? t j = 25 c 6 ? 0.01 5 mv v refloadreg reference variation with load changes, 1 ma < i ref < 5 ma ? t j = 25 c 6 ? 1.6 7 mv i ref ? out maximum output current capability 6 5 ? ? ma note: maximum capacitance directly connected to v ref pin must be under 100 nf. delay t del1 turn ? on llc delay after pfc ok signal is asserted ? 10 20 30 ms t del2 turn ? off llc after power good pin goes low (note 3) ? 2 5 8 ms protections r pull ? up on /off pin pull ? up resistor 4 ? 5 ? k t on/off propagation delay from on to off (ml & mu are off) (note 4) 4 ? ? 1 s v on low level input voltage on on /off pin (ncp1910 is enabled) 4 ? ? 1 v v off high level input voltage on on /off pin (ncp1910 is disabled) 4 3 ? ? v v op open voltage on on /off pin 4 ? 7 ? v i pg maximum power good pin sink current capability 3 5 ? ? ma v pg power good saturation voltage for i pg = 5 ma 3 ? ? 350 mv i pgadj input bias current, pgadj pin 7 ? 10 ? na v pgadjh pg comparator hysteresis 7 ? 100 ? mv tsd temperature shutdown (note 4) ? 140 ? ? c tsdhyste temperature hysteresis shutdown ? ? 30 ? c power factor correction gate drive section r poh source resistance @ i drv = ? 100 ma 18 ? 9 20 r pol sink resistance @ i drv = 100 ma 18 ? 6.6 18 t pr gate drive voltage rise time from 1.5 v to 10.5 v (c l = 1 nf) 18 ? 60 ? ns t pf gate drive voltage fall time from 10.5 v to 1.5 v (c l = 1 nf) 18 ? 40 ? ns 3. in normal operation, when the power supply is un ? plugged, the bulk voltage goes down. at a first crossed level, the pg pin opens. later, when the bulk crosses a second level, the llc turns off. there is no timing link between these events, except the bulk capacitor dis charge slope. however , if for an unknown reason the pfc is disabled (fault, short ? circuit), the pg pin immediately opens and if sufficient voltage is still present on the bulk (e.g. in high line condition), the llc will be disabled after a typical time of 5 ms. 4. guaranteed by design. ncp1910 http://onsemi.com 9 electrical characteristics (for typical values t j = 25 c, for min/max values t j = ? 40 c to +125 c, max t j = 150 c, v cc = 12 v unless otherwise noted) symbol unit max typ min pin rating power factor correction regulation block v pref pfc voltage reference ? 2.425 2.5 2.575 v i ea error amplifier current capability 10 ? 30 ? a g ea error amplifier gain ? 100 200 300 s i b bias current @ v fb = v pref 9 0 ? 0.3 a v ctrl v ctrl(max) v ctrl(min) v ctrl maximum control voltage @ v fb = 2 v minimum control voltage @ v fb = 3 v v ctrl = v ctrl(max) ? v ctrl(min) 10 10 10 ? ? 2.7 3.6 0.6 3 ? ? 3.3 v v out l / v pref ratio (v out low detect threshold / v pref ) (note 4) ? 94 95 96 % h out l / v pref ratio (v out low detect hysteresis / v pref ) ? ? 0.5 ? % i vld + i ea source current when (v out low detect) is activated 10 190 230 260 a current sense v s current sense pin offset voltage, (i cs = 100 a) 14 ? 10 ? mv i cs(ocp) over ? current protection threshold 14 185 200 215 a power limit i cs x v lbo over power limitation threshold ? 215 275 335 va i cs(opl1) i cs(opl2) over ? power current threshold (v lbo = 1.8 v, v m = 0 v) over ? power current threshold (v lbo = 3.6 v, v m = 0 v) ? 119 56 153 75 187 99 a pulse width modulation f psw pfc switching frequency 18 58 65 72 khz f psw(fold) minimum switching frequency (v fold = 1.5 v, v ctrl = v ctrl(min) + 0.1 v) 18 34 39 43 khz dc pmax maximum pfc duty cycle 18 ? 97 ? % dc pmin minimum pfc duty cycle 18 ? ? 0 % v ctrl(fold) v ctrl pin voltage to start frequency foldback (v fold = 1.5 v) 10 1.8 2 2.2 v v ctrl(foldend) v ctrl pin voltage as frequency foldback reducing to the minimum (f psw = f psw(fold) , v fold = 1.5 v) 10 1.4 1.6 1.8 v v fold(max) maximum internal fold voltage (note 4) ? 1.97 2 2.03 v line brown ? out detection v lbot line brown ? out voltage threshold 12 0.96 1.00 1.04 v i lboh line brown ? out hysteresis current source 12 6 7 8 a t lbo(blank) line brown ? out blanking time ? 25 50 75 ms t lbo(window) line brown ? out monitoring window (note 4) ? 25 50 75 ms v lbo(clamp) lbo pin clamped voltage if v bo < v lbot during t lbo(blank) (i lbo = 100 a) 12 ? 980 ? mv v lboh hysteresis (v lbot ? v lbo(clamp) ) (note 4) 12 10 35 60 mv i lbo(clamp) current capability of lbo 12 100 ? ? a v lbo(pnp) lbo pin voltage when clamped by the pnp transistor (i lbo = 100 a) 12 0.4 0.7 0.9 v 3. in normal operation, when the power supply is un ? plugged, the bulk voltage goes down. at a first crossed level, the pg pin opens. later, when the bulk crosses a second level, the llc turns off. there is no timing link between these events, except the bulk capacitor dis charge slope. however , if for an unknown reason the pfc is disabled (fault, short ? circuit), the pg pin immediately opens and if sufficient voltage is still present on the bulk (e.g. in high line condition), the llc will be disabled after a typical time of 5 ms. 4. guaranteed by design. ncp1910 http://onsemi.com 10 electrical characteristics (for typical values t j = 25 c, for min/max values t j = ? 40 c to +125 c, max t j = 150 c, v cc = 12 v unless otherwise noted) symbol unit max typ min pin rating power factor correction line brown ? out detection v lbo(pd) pull down v lbo threshold 12 1.8 2 2.2 v t lbo(pdlimit) pull down v lbo time limitation ? 4.5 5 6.1 ms t pfcflag time delay to confirm that v ctrl is the maximum to pull down v lbo ? 2.5 5 7.5 ms t lbo(pdblank) pull down v lbo blanking time ? 55 77 90 ms current modulation i m1 i m2 multiplier output current (v ctrl =v ctrl(max) ? 0.2 v , v lbo = 3.6 v, i cs = 50 a) multiplier output current (v ctrl =v ctrl(max) ? 0.2 v , v lbo = 1.2 v, i cs = 150 a) 11 11 46 15 58 19 72 24.5 a over ? voltage protection v ovp1 internal auto recovery over voltage threshold 9 2.536 2.615 2.694 v v ovp1h hysteresis of internal auto recovery over voltage threshold (note 4) 9 ? 44 60 mv t ovp1 propagation delay (v fb = 108% v pref ) to drive low 9, 18 ? 500 ? ns v ovp2 external latched over voltage threshold 8 2.595 2.675 2.755 v k ovph the difference between v ovp2 and v ovp1 over v pref ((v ovp2 ? v ovp1 )/v pref ) ? ? 2 ? % t delovp2 external latched ovp integrating filter time constant ? ? 20 ? s i b,ovp2 input bias current, ovp2 8 ? 10 ? na under ? voltage protection v uvp(on) /v pref uvp activate threshold ratio 9 4 8 12 % v uvp(off) /v pref uvp deactivate threshold ratio 9 6 12 18 % v uvp(h) uvp lockout hysteresis 9 ? 4 ? % t uvp propagation delay (v fb < 8 % v pref ) to drive low 9 ? 18 ? 7 ? s pfc abnormal t pfcabnormal pfc abnormal delay time (v ctrl = v ctrl(max) or v ctrl = v ctrl(min) ? 0.1 v) ? 1 1.5 2.1 sec llc control section oscillator f lsw,min minimum switching frequency, rt = 70 k on r t pin 2 24.25 25 25.75 khz f lsw switching frequency, dt l = 300 ns, rt = 7 k on r t pin 2 208 245 282 khz f lsw,max maximum switching frequency, dt l = 300 ns, rt = 3.5 k on r t pin 2 424 500 575 khz dc l operating duty ? cycle symmetry 23, 20 48 50 52 % v refrt reference voltage for oscillator charging current generation 2 3.33 3.5 3.67 v r ss discharge switch resistance 1 ? 70 ? ss rst soft ? start reset voltage 1 ? 200 ? mv v skip skip cycle threshold, b version only 16 350 400 450 mv v skip,hyste hysteresis level on skip cycle comparator, b version only 16 ? 50 ? mv 3. in normal operation, when the power supply is un ? plugged, the bulk voltage goes down. at a first crossed level, the pg pin opens. later, when the bulk crosses a second level, the llc turns off. there is no timing link between these events, except the bulk capacitor dis charge slope. however , if for an unknown reason the pfc is disabled (fault, short ? circuit), the pg pin immediately opens and if sufficient voltage is still present on the bulk (e.g. in high line condition), the llc will be disabled after a typical time of 5 ms. 4. guaranteed by design. ncp1910 http://onsemi.com 11 electrical characteristics (for typical values t j = 25 c, for min/max values t j = ? 40 c to +125 c, max t j = 150 c, v cc = 12 v unless otherwise noted) symbol unit max typ min pin rating llc control section drive output t lr output voltage rise ? time @ c l = 1 nf, 10 ? 90% of output signal 23, 20 ? 40 ? ns t lf output voltage fall ? time @ c l = 1 nf, 10 ? 90% of output signal 23, 20 ? 20 ? ns r loh source resistance 23, 20 ? 12 26 r lol sink resistance 23, 20 ? 5 11 dt l dead time, measured between 50% of the rise and fall edge 23, 20 268 327 386 ns i hv,leak leakage current on high voltage pins to gnd (600 vdc) 22, 23, 24 ? ? 5 a protections i boadj input bias current, boadj pin 5 ? 15 ? na v boadjh bo comparator hysteresis 5 ? 100 ? mv t bok bo comparator integrating filter time constant from high to low 5 ? 150 ? s t bonotok bo comparator integrating filter time constant from low to high 5 ? 20 ? s v cs1 current ? sense pin level that resets the soft ? start capacitor 15 0.95 1 1.05 v v cs2 current ? sense pin level that permanently latches off the circuit 15 1.42 1.5 1.58 v t cs propagation delay from vcs1/2 activation to respective action 15 ? ? 500 ns 3. in normal operation, when the power supply is un ? plugged, the bulk voltage goes down. at a first crossed level, the pg pin opens. later, when the bulk crosses a second level, the llc turns off. there is no timing link between these events, except the bulk capacitor dis charge slope. however , if for an unknown reason the pfc is disabled (fault, short ? circuit), the pg pin immediately opens and if sufficient voltage is still present on the bulk (e.g. in high line condition), the llc will be disabled after a typical time of 5 ms. 4. guaranteed by design. ncp1910 http://onsemi.com 12 typical characteristics 8 8.5 9 9.5 10 10.5 11 ? 50 ? 25 0 25 50 75 100 125 v cc(on) and v cc(min) (v) figure 6. v cc(on) and v cc(min) vs. temperature temperature ( c) v cc(on) v cc(min) 7 7.5 8 8.5 9 9.5 10 ? 50 ? 25 0 25 50 75 100 125 temperature ( c) v boot(on) and v boot(min) (v) figure 7. v boot(on) and v boot(min) vs. temperature v boot(on) v boot(min) 0 25 50 75 100 ? 50 ? 25 0 25 50 75 100 125 i startup ( a) temperature ( c) figure 8. i startup vs. temperature 550 650 750 850 950 ? 50 ? 25 0 25 50 75 100 125 temperature ( c) figure 9. i cc7 vs. temperature i cc7 ( a) 4.75 4.85 4.95 5.05 5.15 5.25 ? 50 ? 25 0 25 50 75 100 125 v ref ? out (v) figure 10. v ref-out vs. temperature temperature ( c) 4.987 4.988 4.989 4.99 0123456 v ref ? out @ 25 c (v) temperature ( c) figure 11. v ref-out @ 25 c vs. i ref-out ncp1910 http://onsemi.com 13 typical characteristics 1 1.5 2 2.5 3 ? 50 ? 25 0 25 50 75 100 125 v on and v off (v) temperature ( c) figure 12. v on and v off vs. temperature v on v off 2 4 6 8 10 ? 50 ? 25 0 25 50 75 100 125 temperature ( c) r poh and r pol ( ) figure 13. r poh and r pol vs. temperature r poh r pol 2.4 2.5 2.6 2.7 2.8 ? 50 ? 25 0 25 50 75 100 125 v pref , v ovp1 , and v ovp2 (v) temperature ( c) figure 14. v pref , v ovp1 , and v ovp2 vs. temperature v ovp2 v ovp1 v pref ? 40 ? 35 ? 30 ? 25 ? 20 ? 50 ? 25 0 25 50 75 100 125 i ea(source) ( a) temperature ( c) figure 15. i ea(source) vs. temperature 20 25 30 35 40 ? 50 ? 25 0 25 50 75 100 125 i ea(sink) ( a) temperature ( c) figure 16. i ea(sink) vs. temperature 100 150 200 250 300 ? 50 ? 25 0 25 50 75 100 125 temperature ( c) g ea ( s) figure 17. g ea vs. temperature ncp1910 http://onsemi.com 14 typical characteristics 3.3 3.4 3.5 3.6 3.7 3.8 3.9 ? 50 ? 25 0 25 50 75 100 125 temperature ( c) v ctr(max) (v) figure 18. v ctrl(max) vs. temperature 2.7 2.8 2.9 3 3.1 3.2 3.3 ? 50 ? 25 0 25 50 75 100 125 v ctr (v) temperature ( c) figure 19. v ctrl vs. temperature 190 200 210 220 230 240 250 260 ? 50 ? 25 0 25 50 75 100 125 temperature ( c) i vld + i ea ( a) figure 20. i vld +i ea vs. temperature 185 190 195 200 205 210 215 ? 50 ? 25 0 25 50 75 100 125 temperature ( c) i cs(ocp) ( a) figure 21. i cs(ocp) vs. temperature 120 130 140 150 160 170 180 190 ? 50 ? 25 0 25 50 75 100 125 temperature ( c) i cs(opl1) ( a) figure 22. i cs(opl1) vs. temperature 55 65 75 85 95 ? 50 ? 25 0 25 50 75 100 125 temperature ( c) i cs(opl2) ( a) figure 23. i cs(opl2) vs. temperature ncp1910 http://onsemi.com 15 typical characteristics 58 60 62 64 66 68 70 72 ? 50 ? 25 0 25 50 75 100 125 temperature ( c) f psw (khz) figure 24. f psw vs. temperature 34 36 38 40 42 44 ? 50 ? 25 0 25 50 75 100 125 f psw(fold) (khz) temperature ( c) figure 25. f psw(fold) vs. temperature 0.96 0.98 1 1.02 1.04 ? 50 ? 25 0 25 50 75 100 125 v lbot (v) temperature ( c) figure 26. v lbot vs. temperature 6 6.5 7 7.5 8 ? 50 ? 25 0 25 50 75 100 125 i lboh ( a) temperature ( c) figure 27. i lboh vs. temperature 4 6 8 10 12 14 16 18 ? 50 ? 25 0 25 50 75 100 125 v uv(on) / v pref and v up(off) / v pref (%) temperature ( c) figure 28. v uvp(on) /v pref and v uvp(off) /v pref vs. temperature v uvp(on) / v pref v uvp(off) / v pref 24 24.5 25 25.5 26 ? 50 ? 25 0 25 50 75 100 125 f lsw,min (khz) temperature ( c) figure 29. f lsw,min vs. temperature ncp1910 http://onsemi.com 16 typical characteristics 210 220 230 240 250 260 270 280 ? 50 ? 25 0 25 50 75 100 125 f lsw (khz) temperature ( c) figure 30. f lsw vs. temperature 425 450 475 500 525 ? 50 ? 25 0 25 50 75 100 125 f lsw,max (khz) temperature ( c) figure 31. f lsw,max vs. temperature ? 50 ? 25 0 25 50 75 100 125 3.3 3.4 3.5 3.6 3.7 v refrt (v) temperature ( c) figure 32. v refrt vs. temperature 100 150 200 250 300 ? 50 ? 25 0 25 50 75 100 125 temperature ( c) ss rst (mv) figure 33. ss rst vs. temperature 350 375 400 425 450 ? 50 ? 25 0 25 50 75 100 125 temperature ( c) v skip (mv) figure 34. v skip vs. temperature 2 4 6 8 10 12 14 16 18 20 22 24 ? 50 ? 25 0 25 50 75 100 125 r loh,ml and r lol,ml ( ) temperature ( c) figure 35. r loh,ml and r lol,ml vs. temperature r lol,ml r loh,ml ncp1910 http://onsemi.com 17 typical characteristics 2 4 6 8 10 12 14 16 18 20 22 24 ? 50 ? 25 0 25 50 75 100 125 r loh,mu and r lol,mu ( ) temperature ( c) r lol,mu r loh,mu figure 36. r loh,mu and r lol,mu vs. temperature 300 310 320 330 340 ? 50 ? 25 0 25 50 75 100 125 temperature ( c) dt l (ns) figure 37. dt l vs. temperature 0.95 0.975 1 1.025 1.05 ? 50 ? 25 0 25 50 75 100 125 v cs1 (v) temperature ( c) figure 38. v cs1 vs. temperature 1.4 1.45 1.5 1.55 1.6 ? 50 ? 25 0 25 50 75 100 125 temperature ( c) v cs2 (v) figure 39. v cs2 vs. temperature 20 40 60 80 100 120 140 ? 50 ? 25 0 25 50 75 100 125 temperature ( c) t cs (ns) figure 40. t cs vs. temperature ncp1910 http://onsemi.com 18 application information the ncp1910 represents a new generation of control circuit, associating two individual cores performing the functions of continuous conduction mode (ccm) power factor correction (pfc) and llc resonant control. these cores interact together and implement handshake functions in normal operating conditions but also when a fault appears. based on the on semiconductor proprietary high ? voltage technology, the llc section can drive the high ? side mosfet of the llc half ? bridge without the need of a gate ? drive transformer. power factor correction ? compactness and flexibility : the ncp1910 requires a minimum of external components to perform a ccm pfc operation. in particular, the circuit scheme simplifies the pfc stage design. in addition, the circuit offers some functions like the line brown ? out detection or true power limiting capability that enable the optimization of the pfc design. ? low consumption and shutdown capability : the ncp1910 is optimized to consume a small current in all operation modes. the consumed current is particularly reduced during the start ? up phase and in shutdown mode so that the power losses are minimized when the circuit is disabled. this feature helps meet stringent stand ? by low power specifications. grounding the feed ? back pin can force the circuit to enter standby but the on/off pin can also serve this purpose. ? maximum current limit : the circuit permanently senses the inductor current and immediately turns off the power switch if it is higher than the set current limit. the ncp1910 also prevents any turn on of the power switch as long as the inductor current is not below its maximum permissible level. this feature protects the mosfet from possible excessive stress that could result from the switching of a current higher than the one the power switch is dimensioned for. in particular, this scheme effectively protects the pfc stage during the start ? up phase when large in ? rush currents charge the bulk capacitor. ? under ? voltage protection for open loop protection : the circuit detects when the feed ? back voltage goes below than about 8% of the regulation level. in this case, the circuit turns off and its consumption drops to a very low value. this feature protects the pfc stage from starting operation in case of low ac line conditions or in case of a failure in the feed ? back network (i.e. bad connection). in case the uvp circuitry is activated, the power good signal is disabled and the llc circuit stops immediately. ? fast transient response : given the low bandwidth of the regulation block, the output voltage of pfc stages may exhibit excessive over or under ? shoots because of abrupt load or input voltage variations (e.g. at start up). if the bulk voltage is too far from the regulation level: ? over ? voltage protection : ncp1910 turns off the power switch as soon as v bulk exceeds the ovp threshold (105% of the regulation level). this is an auto ? recovery function. ? dynamic response enhancer : ncp1910 drastically speeds up the regulation loop by its internal 200 a current source, activated when the bulk voltage drops below 95% of its regulation level. ? line brown ? out detection : the circuit detects low ac line conditions and disables the pfc stage in this case. this protection mainly protects the power switch from the excessive stress that could damage it in such conditions. ? over ? power limitation : the ncp1910 computes the maximum permissible current in dependence of the average input voltage measured by the brown ? out block. it is the second ocp with a threshold that is line dependent. when the circuit detects an excessive power transfer, it resets the driver output immediately. ? redundant over ? voltage protection : as a redundant safety feature, the ncp1910 offers a second latched ovp whose input is available on ovp2 pin. if the voltage on this pin is above the maximum allowable voltage, the pfc and the lcc are latched off. ? pfc abnormal protection : when pfc faces an abnormal situation so that the bulk voltage is under regulation longer than the allowable timing, the pfc and llc are latched off. ? frequency foldback : in light output loading conditions, the user has the ability to program a point on the v ctrl pin where the oscillator frequency is gradually reduced. this helps to maintain an adequate efficiency on the pfc power stage alone. ? soft ? start : to offer a clean start ? up sequence and limit both the stress on the power mosfet and the bulk voltage overshoot, a 30 a current source charges the compensation network installed on v ctrl pin and makes v ctrl raise gradually. ? output stage totem pole : the ncp1910 incorporates a 1.0 a gate driver to efficiently drive to220 or to247 power mosfets. llc controller ? wide frequency operation : the part can operate to a frequency up to 500 khz by connecting a resistive network from r t pin to ground. one resistor sets the maximum switching frequency whereas a second resistor set the minimum frequency. ncp1910 http://onsemi.com 19 ? on board dead time : to eliminate the shoot ? through on the half ? bridge leg, a dead time is included in the controller (see dt l parameter). ? soft ? start : a dedicated pin discharges a capacitor to ground upon start ? up to offer a smooth output voltage ramp up. the start ? up frequency is the maximum set by the resistor connected between r t pin and ss pin. the capacitor connected from r t pin to ground fixes the soft start duration. in fault mode, when the voltage on cs/ff pin exceeds a typical value of 1 v, the soft ? start pin is immediately discharged and a re ? start at high frequency occurs. ? skip cycle operation : to avoid any frequency runaway in light conditions but also to improve the standby power consumption, the ncp1910b welcomes a skip input (skip pin) which permanently observes the opto ? coupler collector. if this pin senses a low voltage, it cuts the llc output pulses until the collector goes up again. the ncp1910a does not offer the skip capability and routes the analog ground on pin 16 instead. ? high ? voltage drivers : capitalizing on on semiconductor technology, the llc controller includes a high ? voltage section allowing a direct connection to the high ? voltage rail. the mosfet leg can therefore be directly driven without using a gate ? drive transformer. ? fault protection : as explained in the above lines, the cs/ff pin combines a two ? level protection circuit. if the level crosses the first level (1 v), the llc converter immediately increases its switching frequency to the maximum set by the external resistive divider connected on r t pin. this is an auto ? recovery protection mode. in case the fault is more severe, the signal on the cs/ff pin crosses the second threshold (1.5 v) and latches off the whole combo controller. reset occurs via an uvlo detection on v cc , a reset on the on/off pin or a brown ? out detection on the pfc stage. this latter confirms that the user has unplugged and re ? plugged the power supply. combo management ? start ? up delay : the pfc start ? up sequence often generates an output overshoot followed by damped oscillations. to make sure the pfc output voltage is fully stabilized before starting the llc converter, a 20 ms delay is inserted after the internal pfc_ok signal is asserted. this delay is always reset when the combo is started from a vcc ulvo, line brown ? out condition or via the on/off pin. ? power good signal : the power good signal (pg) is intended to instruct the downstream circuitry installed on the isolated secondary side that the combo is working. once the pfc has started, an internal ?pfc_ok? signal is asserted. 20 ms later, the pg pin is brought low. this signal can now disappear in two cases: the bulk voltage decreases to an abnormal level, programmed by a reference voltage imposed on pg adj pin. this level is usually above the llc turn ? off voltage, programmed by bo adj pin. therefore, in a normal turn ? off sequence, pg first drops and signals the secondary side that it must be prepared for shutdown. the second event that can drop the pg signal is when the pfc experiences a fault: broken feedback path, severe overload. in this case, the pg signal is immediately asserted high and a 5 ms timer starts. once this timer is elapsed, the llc converter can be safely halted. ? latched event : in the event of a severe operating condition, the pfc can be latched (ovp2 pin) and/or the llc controller also (cs/ff pin). in either case, the whole combo controller is locked and can only be reset via a v cc uvlo, line brown ? out or a level transition on pin on/off. ? thermal shutdown : an internal thermal circuitry disables the circuit gate drive and then keeps the power switch off when the junction temperature exceeds 140 c typically. the circuit resumes operation once the temperature drops below about 110 c (30 c hysteresis). principle of ncp1910 scheme pfc section a ccm pfc boost converter is shown in figure 41. the input voltage is a rectified 50 hz or 60 hz sinusoidal signal. the mosfet is switching at a high frequency (typically 65 khz in ncp1910) so that the inductor current i l basically consists of high and low ? frequency components. filter capacitor c in is an essential and very small value capacitor in order to eliminate the high ? frequency component of the inductor i l . this filter capacitor cannot be too bulky because it can pollute the power factor by distorting the rectified sinusoidal input voltage. ncp1910 http://onsemi.com 20 c in r sense l i l c bulk v in i in bulk voltage (v bulk ) figure 41. ccm pfc boost converter pfc methodology the ncp1910 uses a proprietary pfc methodology particularly designed for ccm operation. the pfc methodology is described in this section. figure 42. inductor current in ccm as shown in figure 42, the inductor current i l in a switching period t includes a charging phase for duration t 1 and a discharging phase for duration t 2 . the voltage conversion ratio is obtained in equation 1. v bulk v in t 1 t 2 t 2 t t t 1 (eq. 1) v in t t 1 t v bulk where: ? v bulk is the output voltage of pfc stage, ? v in is the rectified input voltage, ? t is the switching period, ? t 1 is the mosfet on time, and ? t 2 is the mosfet off time. the input filter capacitor c in and the front ? ended emi filter absorbs the high ? frequency component of inductor current i l . it makes the input current i in a low ? frequency signal only of the inductor current. i in i l ? 50 (eq. 2) where: ? i in is the input ac current. ? i l is the inductor current. ? i l ? 50 supposes a 50 hz operation. the suffix 50 means it is with a 50 hz bandwidth of the original i l . from equations 1 and 2, the input impedance z in is formulated. z in v in i in t t 1 t v bulk i l 50 (eq. 3) where: z in is input impedance. power factor is corrected when the input impedance z in in equation 3 is constant or varies slowly in the 50 or 60 hz bandwidth. ncp1910 http://onsemi.com 21 figure 43. pfc duty modulation and timing diagram v pref v pref the pfc modulation and timing diagram is shown in figure 43. the mosfet on time t 1 is generated by the intersection of reference voltage v pref and ramp voltage v ramp . a relationship in equation 4 is obtained. v ramp v m i ch t 1 c ramp v pref (eq. 4) where: ? v ramp is the internal ramp voltage, the positive input of the pfc modulation comparator, ? v m is the multiplier voltage appearing on v m pin, ? i ch is the internal charging current, ? c ramp is the internal ramp capacitor, and ? v pref is the internal reference voltage, the negative input of the pfc modulation comparator. i ch , c ramp , and v pref also act as the ramp signal of switching frequency. hence the charging current i ch is specially designed as in equation 5. the multiplier voltage v m is therefore expressed in terms of t 1 in equation 6. i ch c ramp v pref t (eq. 5) v m v pref t 1 c ramp c ramp v pref t v pref t t 1 t (eq. 6) from equation 3 and equation 6, the input impedance z in is re ? formulated in equation 7. z in v m v pref v bulk i l ? 50 (eq. 7) because v pref and v bulk are roughly constant versus time, the multiplier voltage v m is designed to be proportional to the i l ? 50 in order to have a constant z in for pfc purpose. it is illustrated in figure 44. figure 44. multiplier voltage timing diagram it can be seen in the timing diagram in figure 43 that v m originally consists of a switching frequency ripple coming from the inductor current i l . the duty ratio can be inaccurately generated due to this ripple. this modulation is the so ? called ?peak current mode?. hence, an external capacitor c m connected to the multiplier voltage v m pin is essential to bypass the high ? frequency component of v m . the modulation becomes the so ? called ?average current mode? with a better accuracy for pfc. ncp1910 http://onsemi.com 22 11 v m pfc duty modulation r m c m i m figure 45. the multiplier voltage pin configuration v m r m i cs v lbo 2 4 v ctrl v ctrl min the multiplier voltage v m is generated according to equation 8. v m r m i cs v lbo 2 4 v ctrl v ctrl(min) (eq. 8) where: ? r m is the external multiplier resistor connected to v m pin, which is constant. ? v lbo is the input voltage signal appearing on the lbo pin, which is proportional to the rms input voltage, ? i cs is the sense current proportional to the inductor current i l as described in equation 13. ? v ctrl is the control voltage signal, the output voltage of operational trans ? conductance amplifier (ota), as described in equation 17. ? v ctrl(min) is not only the minimum operating voltage of v ctrl but also the offset voltage for the pfc current modulation. r m directly limits the maximum input power capability. also, due to the v in 2 feed ? forward feature, where the v lbo is squared, the transfer function and the power delivery is independent from the ac line level. the relationship between v ctrl and power delivery will be depicted later on. line brown ? out protection emi filter ac line r q s l reset reset reset bo vdd v in r lbou r lbol c in r sense c lbo pfc_bo v lbot i lboh lbo comp. v lbocomp t lbo(blank) t lbo(window) v lbo(clamp) lbo figure 46. the line brown ? out configuration as shown in figure 46, the line brown ? out pin (represented lbo pin) as receives a portion of the input voltage (v in ). as v in is a rectified sinusoid, a capacitor must integrate the ac line ripple so that a voltage proportional to the average value of v in is applied to the brown ? out pin. the main function of the lbo block is to detect too low input voltage conditions. a 7 a current source lowers the lbo pin voltage when a brown ? out condition is detected. this is for hysteresis purpose as required by this function. in nominal operation, the voltage applied to lbo pin must be above the internal reference voltage, v lbot (1 v typically). in this case, the output of the lbo comparator v lbocomp is low. ncp1910 http://onsemi.com 23 conversely, if v lbo goes below 1 v, v lbocomp turns high and a 980 mv voltage source, v lbo(clamp) , is connected to the lbo pin to maintain the pin level near 1 v. then a 50 ms blanking delay, t lbo(blank) , is activated during which no fault is detected. the main goal of the 50 ms lag is to help meet the hold ? up requirements. in case of a short mains interruption, no fault is detected and hence, both pfc and llc keep operating. in addition, lbo pin being kept at 980 mv, there is almost no extra delay between the line recovery and the occurrence of a proper voltage applied to lbo pin, that otherwise would exist because of the large capacitor typically placed between lbo pin and ground to filter the input voltage ripple. as a result, the ncp1910 effectively ?blanks? any mains interruption that is shorter than 25 ms (minimum guaranteed value of the 50 ms timer). at the end of this blanking delay (t lbo(blank) ), another timer is activated that sets a 50 ms window during which a fault can be detected. this is the role of the t lbo(window) in figure 46: ? if v lbocomp is high during the second 50 ms delay (t lbo(window) ), a line brown ? out condition is confirmed and pfc_bo signal is asserted high. ? if v lbocomp remains low for the duration of the t lbo(window) , no fault is detected. when the pfc_bo signal is high: ? the pfc driver is disabled, and the v ctrl pin is grounded to recover operation with a soft ? start when the fault has gone. ? the v lbo(clamp) voltage source is removed from lbo pin. ? the i lboh current source (7 a typically) is enabled that lowers the lbo pin voltage for hysteresis purpose. at startup, a pnp transistor ensures that the lbo pin voltage remains below when: v cc < uvlo or on/off pin is released open or uvp or thermal shutdown. this is to guarantee that the circuit starts operation in the right state, which is ?pfc_bo? high. when the ncp1910 is ready to work, the pnp transistor turns off and the circuit enables the i lboh . also, i lboh is enabled whenever the part is in off mode, but at startup, i lboh is disabled until v cc reaches v cc(on) . line brown ? out network calculation if the line brown ? out network is connected to the voltage after bridge diode, the monitored voltage can be very different depending on the phase: ? before operation, the pfc stage is off and the input bridge acts as a peak detector. as a consequence, the input voltage is approximately flat and nearly equates the ac line amplitude: r lbou r lbol r lbou r lbol v lbo 2 v ac,rms r lbol r lbou r lbol i lboh r lbol if r lbol << r lbou , ? after the pfc stage has started operation, the input voltage becomes a rectified sinusoid and the average voltage becomes 2 v ac,on v ac,off 1 v lbot i lboh (eq. 11) 1 0.967 2 v ac,on v ac,off 1 v lbot i lboh r lbou 2 v ac,on i lboh r lbol v lbot 1 r lbol (eq. 12) where: ncp1910 http://onsemi.com 24 ? v ac,on is the rms ac voltage to starts pfc operating. ? v ac,off the rms ac voltage for line brown ? out detection. pfc current sense gnd cs ncp1910 i cs r cs r sense i l + ? v cs i l figure 47. pfc current sensing configuration the device senses the inductor current i l by the current sense scheme in figure 47. the device maintains the voltage at cs pin to be zero voltage, i.e. v cs = 0 v, so that i cs r sense r cs i l (eq. 13) where: ? r sense is the sense resistor to sense i l . ? r cs is the offset resistor between cs pin and r sense . this scheme has the advantage of the minimum number of components for current sensing. the sense current i cs represents the inductor current i l and will be used in the pfc duty modulation to generate the multiplier voltage v m , over ? power limitation (opl), and over ? current protection. equation 13 would insist in the fact that it provides the flexibility in the r sense choice and that it allows to detect in ? rush currents. pfc over ? current protection (ocp) pfc over ? current protection is reached when i cs is larger than i s(ocp) (200 a typical). the offset voltage of the cs pin is typical 10 mv and it is neglected in the calculation. hence, the maximum ocp inductor current threshold i l(ocp) is obtained in equation 14. i l ocp r cs i s ocp r sense r cs r sense 200 a (eq. 14) when over ? current protection threshold is reached, the pfc drive goes low. the device automatically resumes operation when the inductor current goes below the threshold. pfc over ? power limitation (opl) this is a second ocp with a threshold that is line dependent. sense current i cs represents the inductor current i l and hence represents the input current approximately. input voltage signal v lbo represents the rms input voltage. the product (i cs x v lbo ) represents an approximated input power (i l x v ac ). it is illustrated in figure 48. current mirror opl v in r sense r cs cs lbo r lbou r lbol c lbo i cs figure 48. pfc over ? power limitation configuration i l > 275 va? when the product (i cs x v lbo ) is greater than a permissible level 275 va, the device turns off the pfc driver so that the input power is limited. the opl is automatically deactivated when the product (i cs x v lbo ) is lower than the 275 va level. this 275 va level corresponds to the approximated input power (i l x vac) to be smaller than the particular expression in equation 15. i cs v lbo 275 va (eq. 15) i l r sense r cs 22 k lbo v ac 275 va i l v ac r cs r s en s e k lb o 97 va where k lbo r lbol r lbou r lbol ncp1910 http://onsemi.com 25 pfc reference section the internal reference voltage (v pref ) is trimmed to be 2% accurate over the temperature range (the typical value is 2.5 v). v pref is the reference used for the regulation of pfc section. pfc feedback and compensation ota v bulk v in r fbu r fbl r z c z c p v ctrl(min) to multiplier of v m pin fb v ctrl v pref figure 49. v ctrl type ? 2 compensation the output voltage v bulk of the pfc circuits is sensed at fb pin via the resistor divider (r fbl and r fbu ) as shown in figure 49. v bulk is regulated as described in equation 16. v bulk v pref r fbu r fbl r fbl (eq. 16) the feedback signal v fb represents the output voltage v bulk and will be used in the output voltage regulation, over ? voltage protection (ovp), fast transient response, and under ? voltage protection (uvp) the operational trans ? conductance amplifier (ota) constructs a control voltage, v ctrl , depending on the output power and hence v bulk . the operating range of v ctrl is from v ctrl(min) to v ctrl(max) . the signal used for pfc duty modulation is after decreasing a offset voltage, v ctrl(min) , i.e. v ctrl ? v ctrl(min) . this control voltage v ctrl is a roughly constant voltage that comes from the pfc output voltage v bulk that is a slowly varying signal. the bandwidth of v ctrl can be additionally limited by inserting the external type ? 2 compensation components (that are r z , c z , and c p as shown in figure 49). it is recommended to limit cross over frequency of open loop system below 20 hz typically if the input ac voltage is 50 hz to achieve power factor correction purpose. the transformer of v bulk to v ctrl is as described in equation 16 if c z >> c p . g ea is the error amplifier gain. v ctrl v bulk r fbl g ea r z r fbl r fbu 1 sr z c z sr z c z 1 sr z c p (eq. 17) pfc power analysis and v in 2 feed ? forward from equation 7 through 13, the input impedance z in is re ? formulated in equation 18. z in 2r m r sense k lbo 2 v ac 2 v bulk i l 2 r cs v ctrl v ctrl min v pref i l ? 50 (eq. 18) when i l is equal to i l ? 50 , equation 18 is re ? formulated in equation 19. z in 2r m r sense k lbo 2 v ac 2 v bulk 2 r cs v ctrl v ctrl min v pref (eq. 19) the multiplier capacitor c m is the one to filter the high ? frequency component of the multiplier voltage v m . the high ? frequency component is basically coming from the inductor current i l . on the other hand, the input filter capacitor c in similarly removes the high ? frequency component of inductor current i l . if the capacitors c m and c in match with each other in terms of filtering capability, i l becomes i l ? 50 . input impedance z in is roughly constant over the bandwidth of 50 or 60 hz and power factor is corrected. input and output power (p in and p out ) are derived in equations 20 and 21 when the circuit efficiency is obtained or assumed. the variable v ac stands for the rms input voltage. p in v ac 2 z in 2 r cs v ctrl v ctrl min v pref 2r m r sense k lbo 2 v bulk (eq. 20) v ctrl v ctrl min v bulk p in p in 2 r cs v ctrl v ctrl min v pref 2r m r sense k lbo 2 v bulk (eq. 21) v ctrl v ctrl min v bulk because of the v in 2 feed ? forward, the power delivery is independent from input voltage. hence the transfer function of power stage is independent from input voltage, which easies the compensation loop design. ncp1910 http://onsemi.com 26 pfc frequency foldback ncp1910 implements frequency foldback feature on pfc section to improve the efficiency at light load. thanks to v in 2 feed ? forward feature, the output power is proportional to the (v ctrl ? v ctrl(min) ). the pfc frequency foldback is hence done by comparing (v ctrl ? v ctrl(min) ) with v fold , the voltage on fold pin. the simplified block diagram of pfc frequency foldback feature is depicted in figure 50. figure 50. the pfc frequency foldback block + ? ?0? / ?1? v pref / 10%v pref oscillator section vref ict(min) ict vfold vfold(max) s r q q pfc ok grand reset pfcosc vdd ict(fold) pfc bo vctrl vctrl(min) where: ? i ct(min) limits the minimum operating frequency. ? i ct and i ct(min) provide the charging current for oscillator and hence control the nominal operating frequency. ? v fold determines the power level at which the frequency foldback starts. ? i ct(fold) steals the i ct and hence reduces the operating frequency according to the error information between v fold and (v ctrl ? v ctrl(min) ). ? the transient slope of frequency foldback vs. v ctrl is fixed inside. ? v fold(max) is to limit the maximum power level of frequency foldback, which is around 2 v typically. the frequency foldback is disabled at startup, i.e. before the pfcok signal in figure 50 is asserted high. the user can adjust the power level at which the frequency foldback starts by adjust the resistor divider between v ref pin and fold pin. also, the frequency foldback can be disabled by grounding fold pin. the relationship between operating frequency and v ctrl is depicted in figure 51. v ctrl ? v ctrl(min) power f sw(fold) f sw v fold v fold ? 0.4 the slope is fixed internally. the power level at which fre- quency starts reducing is ad- justable by modifying v fold . figure 51. the relationship between frequency and v ctrl frequency ncp1910 http://onsemi.com 27 pfc power boost as depicted in previous section, thanks to the v in 2 feed-forward, the power delivery is independent from input voltage. it brings benefit of good power factor and a direct control on the frequency foldback. however, in some special case such as when the ac input voltage drops sharply from high line to low line, the power will be limited because the filter on lbo pin slows down the reaction speed to follow up the change on input voltage. in the end, the bulk voltage might drop too low and stop the llc converter. hence, ncp1910 builds a so-called pfc power boost function inside. the idea is to pull down lbo pin to 2 v typically, v lbo(pd) , when ? v lbo is above 2 v, v lbo(pd) , i.e. the input is at high line, and ? v ctrl is at maximum for more than timer defined by t pfcflag , and, ? v bulk is under 95% of nominal output, i.e. vld is triggered. the maximum pulling-down duration is defined by t lbo(pdlimit) , which is 5 ms typically. a blanking timer, t lbo(pdblank) , is to avoid this power boost function reacting too soon, which is about 77 ms typically. the pfc power boost function is inhibited at start-up until bulk voltage is above 95% of nominal output. pfc skip mode in order to ensure a proper regulation in no load conditions, the circuit skips cycles when v ctrl is at its minimum level. v ctrl is maintained between about 0.6 v and 3.6 v due to the internal active clamps. a skip sequence occurs as long as the 0.6 v clamp circuitry is triggered and switching operations is recovered when the clamp is inactive. fast transient response given the low bandwidth of the regulation block, the output voltage of pfc stages may exhibit excessive over or under ? shoots because of abrupt load or input voltage variations (such as start ? up duration). as shown in figure 52, if the output voltage is out of regulation, ncp1910 has 2 functions to maintain the output voltage regulation. + ? v ctrl fb r fbu r fbl c fb 105% v pref vld pfc_ovp 95% v pref pfc_ok pfc_opl vdd i vld v bulk ota v pref 30 a 200 a figure 52. pfc ovp and vld ? over ? voltage protection (ovp) : when v fb is higher than 105% of v pref (i.e. v bulk > 105% of nominal bulk voltage), the pfc driver output goes low for protection. the circuit automatically resumes operation when v fb becomes lower than 103.2% of v pref , i.e. around 44 mv hysteresis in the ovp comparator. if the nominal v bulk is set at 390 v, then the maximum bulk voltage is 105% of 390 v = 410 v. hence a cost and size effective bulk capacitor of lower voltage rating is suitable for this application, ? voltage ? low detection (vld) : ncp1910 drastically speeds up the regulation loop by its internal 200 a enhanced current source when the bulk voltage is below 95% of its regulation level. under normal condition, the ncp1910 http://onsemi.com 28 maximum sink and source of output current capability of ota is around 30 a. due to the ?v out low detect? block (vld), when the v fb is below 95% v pref , an extra 200 a current source (i vld in figure 52) will raise v ctrl rapidly. hence prevent the pfc output from dropping too low and improve the transient response performance. the relationship between current flowing in/out v ctrl pin and v fb is as shown in figure 53. it is recommended to add a typical 100 pf capacitor c fb decoupling capacitor next to feedback pin to prevent from noise impact. ? 250 ? 200 ? 150 ? 100 ? 50 0 50 2 2.2 2.4 2.6 2.8 3 v fb v ctrl pin current ( a) 230 a raises v ctrl rapidly when v fb is below 95% v pref no drv when v fb is above 105% v pref figure 53. v fb vs. current flowing in/out from v ctrl pin pfcok signal the pfc provides a ?pfcok? signal to: ? enable the dynamic response enhancer (i vld ) if v bulk is below 95%, finish of the pfc soft ? start, ? enable the pfc frequency foldback, ? enable the timer (t del1 ), which is to start the llc ? hb converter, ? enable the timer (t del2 ), which is to stop llc ? hb converter once ?pfcok? is asserted low or v bulk is lower than pg level after llc ? hb has started. this ?pfcok? signal is high when the pfc stage is in normal operation, i.e. its output is above 95% of normal output, and low otherwise. refer to figure 54. ?pfcok? signal is low when ? the pfc stage start ? up, or ? any latch off signal arrives, or ? line brown ? out activates. ?pfcok? signal is high when ? drv starts operating and the pfc stage is above 95% of target, i.e. the vld comparator output is high, or ? the pfc stage is above 100% target, i.e. pfc reg comparator output is high. grand reset pfc_ok latch s r q q pfc_bo + ? + ? fb v pref 95% v pref vld pfc reg drv figure 54. pfcok signal block diagram ncp1910 http://onsemi.com 29 pfc soft ? start refer to figure 52 and 54. the device provides no pfc driver output when the v ctrl is lower than v ctrl(min) . v ctrl is pulled low by: ? v cc under ? voltage lockout, or ? off signal from on/off pin, or ? thermal shut ? down (tsd), or ? line brown ? out, or ? pfc under ? voltage protection at one of these situations, ncp1910 grounds the v ctrl pin and turns off the 200 a current source in regulation block. when the ic turns on again: ? v ctrl will be pulled low and pfc drv output keeps off until v ctrl is below v ctrl(min) to make pfc starts with lowest duty cycle. ? the 200 a current source block keeps off. only the operating transconductance amplifier (ota) raises the v ctrl slowly. this is to obtain a slow increasing duty cycle and hence reduce the voltage and current stress on the mosfet. a soft ? start operation is obtained. pfc under ? voltage protection (uvp) for open loop protection i cc7 i cc2 8% v pref 12% v pref v fb operating shutdown figure 55. pfc under ? voltage protection as shown in figure 55, when v fb is less than 8% of v pref , the device is shut down. the device automatically starts operation when the output voltage goes above 12% of v pref . in normal situation of boost converter configuration, the bulk voltage v bulk is always greater than the input voltage v in and the feedback signal v fb has to be always greater than 8% and 12% of v pref to enable ncp1910 to operate. the main purpose of this under ? voltage protection function is to protect the power stage from damage at feedback loop abnormal, such as v fb is grounded or the feedback resistor r fbu is open. redundant over ? voltage protection (ovp2 pin) except the over ? voltage protection in fb pin, ncp1910 also reserve one dedicated pin, ovp2 pin, for the redundant over voltage protection on bulk voltage. the purpose of this feature is to protect the power components from damage in case of any drift on the feedback resistor. as shown in figure 56, the ovp2 has 3 dif ferences compared to the ovp in fb pin: ? the protection mode provided by ovp2 pin is latch ? off. when ovp2 is triggered, the ncp1910 stays at latch off mode, i.e. both pfc and llc stop. ? a 20 s filter is built ? in after the ovp2 comparator for better noise immunity. ? the reference voltage for this ovp2 comparator is 107% of v pref. the resistance value of r ovpu and r ovpl could be the same as r fbu and r fbl depending on the requirement of ovp2 level. in this case, the level of the ovp in fb pin would be 105% of normal bulk voltage and ovp2 will be 107% of normal bulk voltage. or if one would need a higher level for the ovp2, then it is flexible to change the value. if someone doesn?t need this ovp2 feature, then ovp2 function could be disable by grounding the ovp2 pin. r ovpu r ovpl c ovp 107% v pref pfc_ovp2 v bulk 20 s filter ovp2 to sr-latch figure 56. pfc 2 nd over ? voltage protection ncp1910 http://onsemi.com 30 pfc abnormal the pfc abnormal is detected by sensing v ctrl level. when v ctrl stays at v ctrl(max) , or lower than v ctrl(min) ? 0.1 v, for more than t pfcabnormal , pfc turns of f first. after t del2 , llc shuts down. it is latches off protection. the main purpose of this feature is to avoid llc from operating without correct operation of pfc stage. llc section current controlled oscillator (cco) the current controlled oscillator features a high ? speed circuitry allowing operation from 50 khz up to 1 mhz. however, as a d ? flip ? flop that creates division ? by ? two internally provides two outputs (a and b in figure 57), the final effective signal on llc driver outputs (ml and mu) switches between 25 khz and 500 khz. the cco is configured in such a way that if the current that flows out from the r t pin increases, the switching frequency also goes up. vdd + - s r q q clk d b a grand reset latch llcenable for ml for mu grand reset s r q q grand reset + - s r q q llc_pg grand reset disable llc ml and mu r t ss r min r max r ss c ss feedback opto-coupler c t i dt cs/ff > v cs1 llc_bo t del2 elapsed v ss_rst figure 57. the current controlled oscillator architecture and configuration v rt v ctmax the internal timing capacitor c t is charged by current which is proportional to the current flowing out from the r t pin. the dischar ging current i dt is applied when voltage on this capacitor reaches v ctmax . the output drivers are disabled during discharge period so the dead time length is given by the discharge current sink capability. discharge sink is disabled when voltage on the timing capacitor reaches zero and charging cycle starts again. c t is grounded to disable the oscillator when either of ?turn ? off llc? signals arrives. for the resonant applications, it is necessary to adjust minimum operating frequency with high accuracy. the designer also needs to limit maximum operating and startup frequency. all these parameters can be adjusted by using external components connected to the r t pin as shown in figure 57. the following approximate relationships hold for the minimum, maximum and startup frequency respectively: ncp1910 http://onsemi.com 31 ? the minimum switching frequency is given by the r min resistor value. this frequency is reached if there is no feedback action and soft start period has already elapsed. r min 490 10 6 v rt f min (eq. 22) ? the maximum switching frequency excursion is limited by the r max selection. note that the maximum frequency is influenced by the opto ? coupler saturation voltage value. r max 490 10 6 v rt f max f min (eq. 23) ? resistor r ss together with capacitor c ss prepares the soft start period for the resonant converter. r ss 490 10 6 v rt f ss f min (eq. 24) where: ? v rt = 3.5 v ? f min is the minimal frequency ? f max is the maximal frequency ? f ss is the maximal soft start switching frequency llc power good signal and brown ? out (pg adj , pg out and bo adj pin) as shown in figure 22, the ncp1910 provides the brown ? out circuitry (bo) that offer a way to protect the resonant converter from operating at too low v bulk . in the mean time, ncp1910 provides a power good signal (pg out ) to inform the isolated secondary side that the ncp1910 is in order of match. once the pfc has started and raises v bulk above 95% of its regulated voltage, an internal ?pfc_ok? signal is asserted. 20 ms later (t del1 ), the pg out pin is brought low. the pg out signal can now disappear, which will release pg out pin open, in two cases: ? v bulk decreases to the level, programmed by a reference voltage imposed on pg adj pin. this level is usually above the llc turn ? off voltage, programmed by bo adj pin. therefore, in a normal turn ? off sequence, pg first drops and informs the secondary side that it must be prepared for shutdown. ? the second event that can drop the pg signal is when the pfc experiences a fault: broken feedback path (pfc uvp), pfc abnormal, or input line brown ? out. in either case, the internal pfcok signal will drop and then assert the pg out signal high, and starts a 5 ms timer (t del2 ). once this timer is elapsed, the llc converter can be safely halted. the definition of start ? up, shut ? off and these 2 delay timers (t del1 and t del2 ) will be depicted later in ?combo management section?. there are the other 2 delay timers are built ? in after the brown ? out comparator: ? t bok is the delay timer after v bulk is rising above the bo level. ? t bonotok is the delay timer after v bulk is falling down the bo level. ncp1910 gets the information of v bulk from the pfc fb pin, which minimizes the losses of the high voltage sensing circuit. as depicted in figure 22, 3 resistors (r 1 , r 2 , and r 3 ) among v ref , pg adj , bo adj pin, and ground determine the levels of pg out signal and llc brown ? out as the following formulas: v pg r 2 r 3 r 1 r 2 r 3 v ref (eq. 25) v bulk,pg r fbl r fbu r fbl v bulk,pg v pref v bulk,nom v bo r 3 r 1 r 2 r 3 v ref (eq. 26) v bulk,bo r fbl r fbu r fbl v bulk,bo v pref v bulk,nom where: ? v pg is the voltage on pg adj pin ? v bo is the voltage on bo adj pin ? v ref is the reference voltage (5 v typically). ? v pref is the internal reference voltage for pfc feedback ota (2.5 v typically) ? v bulk,pg is the bulk voltage when pg out pin is released open. ? v bulk,bo is the bulk voltage when brown ? out function of llc activates. ? v bulk,nom is the normal bulk voltage, e.g. 390 v. divide equation 25 by 26, we can get the relationship between r 2 and r 3 in equation 27: r 2 r 3 v bulk,pg v bulk,bo 1 (eq. 27) hence, by given v bulk,pg and v bulk,bo , and choose the value r 3 as the 1 st step, we can get the r 2 by equation 27 and r 1 by equation 26. for example, v bulk,nom is 390 v, v bulk,pg is 340 v, and v bulk,bo is 330 v. choose 10 k resistor as r 3 . then r2 is 303 . choose 300 as it is the closet standard resistor. then we can get the r 1 is 13.3 k . ncp1910 http://onsemi.com 32 pfc_fb ?1? bonotok ?1? enables llc ?0? llc is locked grand reset llc_bo r pfc_ok ?1? is ok ?0? notok r ?1? after reset ?0? when pg out drops after 5 ms llc_bo ?1? pgnotok + ? + ? llc_pg llcenable v ref boadj pgadj pgout r 1 r 2 r 3 v cc v sb pgi for supervisory t bok t bonotok t del1 t del2 20 ms 5 ms to close switch at ss pin ss is reset figure 58. the pg and bo block diagram for llc llc fast fault input (cs/ff pin) as shown in figure 59, the ncp1910 offers a dedicated input (cs/ff pin) to detect the primary over ? current conditions and protect the power stage from damage. once the voltage on the cs/ff pin exceeds the threshold of v cs1 (1 v typically), the internal switch at ss pin will be closed to discharge c ss until v ss is below v ss_rst (150 mv typically). hence the switching frequency of llc (ml and mu) is shifted up to keep the primary current under acceptable level. in case of heavy overload, like transformer short circuit, the primary current grows very fast and thus could reach danger level. the ncp1910 therefore features additional comparator v cs2 (1.5 v typically) at the cs/ff pin to permanently latch the device (both pfc and llc) and protect against destruction. ncp1910 http://onsemi.com 33 + ? s r q q grand reset latch ?1? to disable llc and pfc driver, and pull down pfcok + ? ?1? to set the sr ? latch to pull low ss pin pfc_bo cs/ff v cs1 v cs2 pfc_ovp2 figure 59. the fast fault input at cs/ff pin llc soft ? start (ss pin) in resonant converter, a soft ? start is needed to avoid suddenly applying the full current into the resonating circuit. ncp1910 reserves ss pin to fully discharge soft ? start capacitor before re ? start and in case of fault conditions: ? llc brown ? out actives, ? t del2 is elapsed, where t del2 timer could be activated by line brown ? out or power good comparator, ? cs/ff pin is above v cs1 , the fast fault input for llc, ? v cc uvlo, ? pfc uvp, ? off signal from on/off pin, or ? thermal shut ? down (tsd) when the switch inside ss pin is activated to discharge the soft ? start capacitor, it keeps close until v ss is below v ss_rst (150 mv typically). it ensures the full discharge of soft ? start capacitor before re ? start, and hence the fresh soft ? start is confirmed. once the llc part starts operation, the internal switch at ss pin is released open and the empty soft ? start capacitor withdraws current from r t pin through soft ? start resistor, r ss . this current charges up and soft ? start capacitor and increases the operating frequency of llc. as the soft ? start capacitor is charged, the llc driver output frequency smoothly decreases down to f min . of course, practically, the feedback loop is supposed to take over the cco lead as soon as the output voltage has reached the target. llc skip (skip pin, b version only) to avoid any frequency runaway in light conditions but also to improve the standby power consumption, the ncp1910b welcomes a skip mode operation (skip pin) which permanently observes the opto ? coupler collector as depicted in figure 60. if skip pin senses a low voltage, it cuts the llc output pulses (ml and mu pins) until the collector goes up again. + ? r t ss r min r max r ss c ss feedback opto ? coupler skip v skip disable ml and mu figure 60. the llc skip mode configuration ncp1910 http://onsemi.com 34 llc high ? voltage driver the ncp1910 includes a high ? voltage driver allowing a direct connection to the upper side mosfet of llc converter. this device also incorporates an upper uvlo circuitry that makes sure enough gate voltage is available for the upper side mosfet. the bias of the floating driver section is provided by c boot capacitor between v boot pin and hb pin that is refilled by external booststrap diode. the floating portion can go up to 600 vdc and makes the ic perfectly suitable for offline applications featuring a 400 v pfc front ? end stage. combo management section start ? up and stop delay of llc and pgout signal (t del1 and t del2 ) to ensure the proper operation of llc, llc cannot start if the pfc is not ready. as depicted in the ?pfcok signal? section, the internal pfcok signal is asserted high when v bulk is above 95% of normal bulk voltage. after pfcok signal is high, a timer (t del1 ) starts to ensure pfc stage is fully stable before llc starts. when t del1 is elapsed, pg out pin is grounded and llc starts its driver outputs (ml and mu pins). in case of shutdown by unplugging ac input or line brown out situation, pg out signal is released open. and then another timer (t del2 ) starts. once the t del2 is elapsed, llc stops its drivers (ml and mu pins). figure 61 depicts the start ? up and stop delay of llc and pg out . once the pfc is ready (pfcok is asserted high), t del1 (20 ms typically) is started. once this delay is elapsed: ? pg out pin is asserted low ? llc drivers (ml and mu pins) can start to operate. as shutdown by unplug ac input, v bulk decreases: ? when it reaches the pg signal, which is adjusted by pg adj pin, pg out pin is released open. ? if v bulk reaches the llc stop level (bo level adjusted by bo adj pin), the llc stops; or if v bulk drops slowly, e.g. light load, llc drivers (ml and mu pins) will stop 5 ms after pg out pin is released (t del2 ). as shutdown by line brown ? out situation, pfcok signal will be pulled down: ? pg out pin is released open once this internal pfcok signal is low. ? llc drivers (ml and mu pins) will stop 5 ms after pg out pin is released open (t del2 ). v bulk time 95% llc works off off t del1 t del2 5 ms pg level 20 ms pg out bo level figure 61. the timing for t del1 and t del2 remote on/off (on/off pin) ncp1910 reserves one dedicated pin for remote control feature at on/off pin: ? when the on/off pin is pulled below 1 v, the pfc starts operation. 20 ms after v bulk is above 95% of target level, llc starts. ? when the on/off pin is above 3 v, the device stops both pfc and llc immediately and keeps low consumption. figure 62 depicts the relationship between the operation mode and on/off pin. ncp1910 http://onsemi.com 35 on/off pin state on v on v off on/off pin i cc tbd < 600 a off figure 62. remote on/off (on/off pin) v cc under ? voltage lockout (uvlo) the device incorporates an under ? voltage lockout block to prevent the circuit from operating when v cc is too low in order to ensure a proper operation. an uvlo comparator monitors v cc pin voltage to allow the ncp1910 to operate when v cc exceeds v cc(on) . the comparator incorporates some hysteresis (v cc(hys) ) to prevent erratic operation as the v cc crosses the threshold. when v cc goes below the uvlo comparator lower threshold (v cc(min) ), the circuit turns off. it is illustrated in figure 63. after startup, the operating range is between 9 v and 20 v. v cc state on v cc(min) v cc(on) i cc tbd < 100 a off figure 63. v cc under ? voltage lockout (uvlo) v cc bias the controller it is recommended to add a typical 1 nf to 100 nf decoupling capacitor next to the v cc pin for proper operation. the hysteresis between v cc(on) and v cc(min) is small because the ncp1910 is supposed to be biased by external power source. therefore it is recommended to make a low ? voltage source to bias ncp1910, e.g. the standby power supply. thermal shutdown an internal thermal circuitry disables the circuit gate drive and then keeps the power switch off when the junction temperature exceeds tsd level. the output stage is then enabled once the temperature drops below typically 110 c (i.e. tsd ? tsd hyste ). the thermal shutdown is provided to prevent possible device failures that could result from an accidental over ? heating. 5 v reference the v ref pin provides an accurate ( 2% typically) 5 v reference voltage. the power ? good and brown ? out of llc converter, and the frequency foldback level (fold pin) of pfc can hence can get an accurate reference voltage by resistor dividers. ncp1910 http://onsemi.com 36 latched protections and reset as depicated in the above sections, there are 3 fault modes that latch off both pfc and llc: ? pfc abnormal ? pfc ovp2 ? llc cs/ff pin is above v cs2 to release from the latch ? off mode, ncp1910 offers 3 ways: ? recycle v cc so that v cc is below v cc(min) and back to above v cc(on) again. ? recycle the remote on/off function, which toggles on/off pin high and low again. ? recycle the line brown ? out function, which could be done by unplug and re ? plug the ac input. ordering information device version marking package shipping ? ncp1910a65dwr2g 65 khz ? a ncp1910a65 soic 24wb less pin 21 (pb ? free) 1000 / tape & reel NCP1910B65DWR2G 65 khz ? b ncp1910b65 soic 24wb less pin 21 (pb ? free) 1000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. ncp1910 http://onsemi.com 37 package dimensions soic ? 24 wb less pin 21 case 752ab ? 01 issue o b e m 0.25 c seating plane a1 e m l detail a end view h notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b does not include dambar protrusion. allowable protrusion shall be 0.10 mm total in excess of ?b? at maxim- um material condition. 4. dimensions b and c apply to the flat sec- tion of the lead and are measured between 0.10 and 0.25 from the lead tip. 5. dimensions d and e1 do not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15 mm per side. interlead flash or protrusion shall not exceed 0.25 per side. dimensions d and e1 are determined at datum h. 6. dimensions d and e1 are determined at the outermost extremes of the plastic body exclusive of mold flash, protrusions, tie bar burrs, or gate burrs but inclusive of any mold mismatch between the top and bottom of the plastic body. 7. dimensions a and b are to be determined at datum h. 8. a1 is defined as the vertical distance from the seating plane to the lowest point on the package body. 9. this chamfer is optional. if it is not present, then a pin 1 identifier must be located in the indicated area. l2 notes 3 & 4 pin 1 12 1 24 13 top view dim min max millimeters a 2.35 2.65 b 0.31 0.51 e 1.27 bsc h 0.25 0.75 j 0.20 0.33 a1 0.10 0.29 l 0.40 1.27 m 0 8 d e1 side view 11.00 23x 0.52 23x 1.62 1.27 dimensions: millimeters 1 pitch *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* d 15.40 bsc e 10.30 bsc e1 7.50 bsc l2 0.25 bsc recommended d indicator a-b d note 7 0.10 c d 0.33 c 0.20 c a-b notes 5 & 6 24x 2x 2x b a note 7 2x 0.10 c c a note 8 0.10 c x 45 c note 9 detail a c h on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 ncp1910/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative |
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